The present invention relates in general to cell based integrated circuits such as gate arrays, and in particular to an improved cell architecture and routing scheme for such circuits.
Standard cell or gate array technology have been developed as quick-turn integrated circuit (IC) design methodologies in which pre-designed circuit units or cells (e.g., NAND and NOR gate, Flip-Flops, etc.) are wired together to rapidly implement a new IC functionality. The pre-designed circuit elements are called macro cells which are made by interconnecting basic cells. The design and characteristics of the macro cells typically do not change from one design to the next. It is how these macro cells are interconnected that varies depending on the functionality being implemented.
The interconnect layers in gate arrays perform two functions: they connect basic cells to form macro cells, and, they interconnect macro cells using global routes to implement the desired IC function. A balanced allocation of routing resources is necessary between the need to minimize the area occupied by macro cells and the need to provide sufficient global routing resources to interconnect the maximum number of macro cells on an IC.
The present gate array technology has evolved from two levels of interconnect. The two levels of routing resources have typically been used in orthogonal directions to achieve the highest circuit density. The first and second level routing resources are generally called M1 and M2 respectively. FIG. 1 shows a two level routing scheme according to prior art where M1 tracks 11 are used to route horizontal X direction, and M2 tracks 12 are used in the vertical Y direction. As the technology evolved to three or more levels of interconnect layer, the orthogonality of neighboring levels has been maintained in the prior art. So the third layer M3 is routed in the X direction, parallel to M1 and orthogonal to M2, etc.
The circuit functionality is obtained by interconnecting macro cells 13 which represent different logic functions such as NAND, NOR, Latch, etc. The macro cells 13 are designed to use as much internal M1 routing 14 as possible with occasional use of internal M2 tracks 15, when M1 alone is not sufficient. This arrangement allows many of the M2 global routes 12 to cross over macro cells 13 as shown in FIG. 1. Global M1 tracks 11 in general can not cross over macro cell so they have to be routed adjacent to the macro cells. A third interconnect layer M3 and subsequent interconnect layers can cross over macro cells as long as the macro cells do not use those layers for internal routing. Therefore, the basic cells must be designed with the necessary number of M1 tracks required for internal routing of macro cells. For most frequently used CMOS gate array basic cells, a typical number is about 12.
Furthermore, in the case where a third level of interconnect M3 is available, the prior art approach as shown in FIG. 1 typically uses first and third interconnect layers M1 and M3 in parallel, while the second interconnect layer M2 is disposed orthogonal to them. In the prior schemes, the second interconnect layer M2 is typically used for global routing, power distribution and routing internal to the macro cells. Therefore, there are less global routing tracks available in the M2 direction than M3, causing an imbalanced situation with respect to routing resources. In such cases, the routability of the designs is limited by the M2 tracks.
FIG. 2 shows a prior art basic cell from U.S. Pat. No. 4,884,118 issued to Hui et al., and assigned to LSI Logic Corporation. The basic cell consists of a P-type diffusion region 21 and an N type diffusion region 22, gate electrodes 23, and contact regions 24 for contacting the transistor source/drain/gate terminals. The basic cell also contains regions 28 for contacting the P and N type substrate. Twelve M1 tracks 25 and 29 are provided in the X direction for macro cell routing. Specific M1 tracks 29 are used to connect power supply voltages Vdd and Vss to the transistors. In the Y direction, three M2 tracks 26 are provided for global routing and an additional track 27 for further power supply connection. Track 27 is shared between two adjacent basic cells.
A 2-input NAND gate can be formed from a single basic cell as shown in FIG. 3. First layer tracks 32 and 33 connect Vdd and Vss to the 2-input NAND macro cell. First layer 34 is used to connect two P-type transistor to one N-type transistor. Connections 31 are used to connect the gate electrodes. Vdd and vss also contact to the substrate via contacts 35. The inputs and output of the 2-input NAND are interconnected to other gates using global routes.
Larger functions such as a 4-input NAND gate or a D-Flip-flop require more than one basic cell. An example of a large macro cell 41 containing six basic cells is shown in FIG. 4. All of the basic cells are arranged in the X direction. First level M1 layer is used to interconnect basic cells in both X, as well as Y directions within the macro cell 41. Therefore, first level global routes 44 can be placed only outside of the macro cell. However, second layer internal tracks 43 are used only sparingly inside a macro cell and that also only in the vertical direction. Thus, many of the second layer global routes are free to run through the macro cell in places where there is no second layer blockage, such as tracks 46.
In the above example about ten M1 interconnect tracks are required in the X direction to form a complex macro cell. In addition to the macro cell interconnect resources, additional routing resources (two M1 tracks) are required to distribute power (Vdd) and ground (Vss) to the basic cells. Thus, a total of 12 routing tracks are required, which determines one of the dimensions of the basic cell. In the other direction, at least three tracks are required to contact the source/drain of the two transistor pairs. In addition, one vertical track is required to connect power/ground to the silicon substrate which is shared between a pair of adjacent basic cells. Thus, the overall basic cell is made large enough to allow twelve tracks in X direction and three and a half tracks in Y direction. In this example, it is not possible to make the cell dimensions smaller without significant loss in the macro cell routability.
The large vertical size of the cell results in larger transistors (about four tracks high). This translates to more power consumption per basic cell, and higher load capacitances that slow down the circuits.
Several variations to the above basic cell have been proposed. For example, the horizontal power and ground routes can be shared between adjacent rows of basic cells to reduce the number of horizontal tracks from twelve to eleven. Also, by placing the substrate contact outside the basic cell and under the shared power and ground tracks, the cell width is reduced from 3.5 to 3. However, the cell is still eleven tracks high and has higher resistance in series with the power supply.
In an another variation disclosed in U.S. Pat. No. 5,079,614 issued to M. Khatkhotan and assigned to S-MOS Systems inc., the gate electrodes are interleaved with respect to the diffusion regions to achieve better routability. However, the basic cell in this case is still over ten tracks by nine tracks, or ninety grid points. In a publication by Y. Okuno et al titled, "0.8 .mu.m 1.4 million transistor CMOS SOG based on column macro cell", the authors disclose a novel basic cell and routing approach where the direction of first layer routes is made parallel to the gate electrodes, as opposed to perpendicular as in other prior art. The result is claimed to provide better global routing. The basic cell size, however, is 11.times.9 tracks, or 121 grid points.
Other prior art patents and publications such as U.S. Pat. No. 4,884,115 have disclosed basic cells in which additional small transistors are included to optimize implementation of static random access memory (SRAM) cells. These cells are significantly larger than the four transistor basic cell of FIG. 2. Similarly, inclusion of a bipolar transistor in addition to CMOS transistors is disclosed in U.S. Pat. No. 5,072,285 issued to Ueda et al. Such basic cell allows formation of BiCMOS macro cells comprising of both CMOS and bipolar transistors. These BiCMOS cells again are significantly larger than pure CMOS basic cells.
In U.S. Pat. No. 5,289,021 issued to El Gamal, and assigned to SiArc Inc., three different sized transistors of P and N type are included in the basic cell. Such a cell allows more efficient design of certain large macro cells such as D flip-flop or latch. The basic cell in this case is about 11 tracks by 11 tracks, or 121 grid points. The large basic cell takes up more area and reduces the granularity of the cell placement on the IC.
All of the above prior art is based on orthogonal arrangement of first and second level tracks. This avoids the blockage of second level tracks that run orthogonal to the macro cells. Since only first level tracks are used for horizontal routing of macro cells, the basic cell must provide eleven to twelve tracks in the horizontal direction, resulting in a large basic cell.
There is a need for more compact cell architectures and more flexible routing schemes in cell based circuits.